High yield sub-0.1&#x00B5;m<sup>2</sup> 6T-SRAM cells, featuring high-k/metal-gate finfet devices, double gate patterning, a novel fin etch strategy, full-field EUV lithography and optimized junction design &amp; layout
Naoto Horiguchi(IMEC), S. Biesemans(IMEC), Michał Rakowski(IMEC), G. Mannaert(IMEC), Wilfried Alaerts(IMEC), Geert Vandenberghe(IMEC), Vincent Truffert(IMEC), S. Locorotondo(IMEC), A. Lauwers(IMEC), Johan De Backer(IMEC), C. Huffman(IMEC), S. Brus(University of Liège), Andriy Hikavyy(IMEC), Herbert Struyf(IMEC), M. Demand(IMEC), C. Vrancken(IMEC), Christie Delvaux(IMEC), Kristof Kellens(IMEC), Frédéric Lazzarino(IMEC), N. Heylen(IMEC), Jan Hermans(IMEC), J. Verluijs(IMEC), Patrick Ong(IMEC), Harold Dekkers(IMEC), Kris Baert(Ghent University), P. Absil(IMEC), T. Vandeweyer(IMEC), S. Demuynck(IMEC), Monique Ercken(IMEC), T. Hoffman(IMEC), E. Altamirano(IMEC), Staf Verhaegen(IMEC), Henny Volders(IMEC), Gerald Beyer(IMEC), Kurt Ronse(IMEC)
Cited by 8
Related Papers
Benchmarking SOI and bulk FinFET alternatives for PLANAR CMOS scaling succession
|Solid-State Electronics|2010|120
IR bolometers made of polycrystalline silicon germanium
|Sensors and Actuators A Physical|1998|93
An InGaAs/InP quantum well finfet using the replacement fin process integrated in an RMG flow on 300mm Si substrates
|Unknown|2014|90
Channel Hot Carrier Degradation Mechanism in Long/Short Channel $n$-FinFETs
|IEEE Transactions on Electron Devices|2013|90