Demonstration of scaled 0.099&#x00B5;m<sup>2</sup> FinFET 6T-SRAM cell using full-field EUV lithography for (Sub-)22nm node single-patterning technologyA. Veloso, S. Biesemans, S. Demuynck et al.|Unknown|2009Cited by 14
Integration of tall triple-gate devices with inserted-Ta/sub x/N/sub y/ gate in a 0.274μm/sup 2/ 6t-sram cell and advanced CMOS logic circuitsLiesbeth Witters, S. Biesemans, Jean‐François de Marneffe et al.|Unknown|2005Cited by 12
Ge oxide scavenging and gate stack nitridation for strained Si<sub>0.7</sub>Ge<sub>0.3</sub> pFinFETs enabling 35% higher mobility than SiHiroaki Arimura, Naoto Horiguchi, Kurt Wostyn et al.|Unknown|2019Cited by 10
Full-field EUV and immersion lithography integration in 0.186&#x03BC;m<sup>2</sup> FinFET 6T-SRAM cellA. Veloso, Thomas Hoffmann, S. Demuynck et al.|Unknown|2008Cited by 9
High yield sub-0.1&#x00B5;m<sup>2</sup> 6T-SRAM cells, featuring high-k/metal-gate finfet devices, double gate patterning, a novel fin etch strategy, full-field EUV lithography and optimized junction design &amp; layoutNaoto Horiguchi, S. Biesemans, S. Demuynck et al.|Unknown|2010Cited by 8