Gate-last vs. gate-first technology for aggressively scaled EOT logic/RF CMOSA. Veloso, Thomas Hoffmann, Geert Eneman et al.|Symposium on VLSI Technology|2011Cited by 31
Atomic Layer Deposition of High-κ Dielectrics on Sulphur-Passivated GermaniumSonja Sioncke, Matty Caymax, H. C. Lin et al.|Journal of The Electrochemical Society|2011Cited by 21
Atomic layer deposition of Al2O3 on S-passivated GeSonja Sioncke, Matty Caymax, J. Ceuppens et al.|Microelectronic Engineering|2011Cited by 19
S-passivation of the Ge gate stack: Tuning the gate stack properties by changing the atomic layer deposition oxidant precursorSonja Sioncke, Matty Caymax, Hang-Chun Lin et al.|Journal of Applied Physics|2011Cited by 19
Demonstration of scaled 0.099&#x00B5;m<sup>2</sup> FinFET 6T-SRAM cell using full-field EUV lithography for (Sub-)22nm node single-patterning technologyA. Veloso, S. Biesemans, S. Demuynck et al.|Unknown|2009Cited by 14