Gate-last vs. gate-first technology for aggressively scaled EOT logic/RF CMOSA. Veloso, Thomas Hoffmann, H. Bender et al.|Symposium on VLSI Technology|2011Cited by 31
Process control & integration options of RMG technology for aggressively scaled devicesA. Veloso, Naoto Horiguchi, Yuichi Higuchi et al.|Unknown|2012Cited by 21
Demonstration of scaled 0.099&#x00B5;m<sup>2</sup> FinFET 6T-SRAM cell using full-field EUV lithography for (Sub-)22nm node single-patterning technologyA. Veloso, S. Biesemans, S. Demuynck et al.|Unknown|2009Cited by 14
Dual-channel technology with cap-free single metal gate for high performance CMOS in gate-first and gate-last integrationLiesbeth Witters, Naoto Horiguchi, Jérôme Mitard et al.|Unknown|2011Cited by 12
Highly scalable effective work function engineering approach for multi-V T modulation of planar and FinFET-based RMG high-k last devices for (Sub-)22nm nodesA. Veloso, Naoto Horiguchi, G. Boccardi et al.|Unknown|2013Cited by 9