Low temperature source/drain epitaxy and functional silicides: essentials for ultimate contact scalingClément Porret, Naoto Horiguchi, J.-L. Everaert et al.|2022 International Electron Devices Meeting (IEDM)|2022Cited by 19
Effective Work Function Engineering for Aggressively Scaled Planar and Multi-Gate Fin Field-Effect Transistor-Based Devices with High-k Last Replacement Metal Gate TechnologyA. Veloso, Naoto Horiguchi, Soon Aik Chew et al.|Japanese Journal of Applied Physics|2013Cited by 16
Demonstration of scaled 0.099&#x00B5;m<sup>2</sup> FinFET 6T-SRAM cell using full-field EUV lithography for (Sub-)22nm node single-patterning technologyA. Veloso, S. Biesemans, S. Demuynck et al.|Unknown|2009Cited by 14
Integration of tall triple-gate devices with inserted-Ta/sub x/N/sub y/ gate in a 0.274μm/sup 2/ 6t-sram cell and advanced CMOS logic circuitsLiesbeth Witters, S. Biesemans, M. Van Hove et al.|Unknown|2005Cited by 12
Full-field EUV and immersion lithography integration in 0.186&#x03BC;m<sup>2</sup> FinFET 6T-SRAM cellA. Veloso, Thomas Hoffmann, S. Demuynck et al.|Unknown|2008Cited by 9