(Invited) Vertical Nanowire FET Integration and Device AspectsA. Veloso, Aaron Thean, Efrain Altamirano Sánchez et al.|ECS Transactions|2016Cited by 50
Junctionless gate-all-around lateral and vertical nanowire FETs with simplified processing for advanced logic and analog/RF applications and scaled SRAM cellsA. Veloso, Aaron Thean, Bertrand Parvais et al.|Unknown|2016Cited by 37
Challenges and opportunities of vertical FET devices using 3D circuit design layoutsA. Veloso, Monique Ercken, W. Li et al.|Unknown|2016Cited by 17
Vertical nanowire FET integration and device aspectsA. Veloso, Aaron Thean, Efrain Altamirano Sánchez et al.|Unknown|2016Cited by 14
Demonstration of scaled 0.099&#x00B5;m<sup>2</sup> FinFET 6T-SRAM cell using full-field EUV lithography for (Sub-)22nm node single-patterning technologyA. Veloso, S. Biesemans, S. Demuynck et al.|Unknown|2009Cited by 14