High yield sub-0.1&#x00B5;m<sup>2</sup> 6T-SRAM cells, featuring high-k/metal-gate finfet devices, double gate patterning, a novel fin etch strategy, full-field EUV lithography and optimized junction design &amp; layoutNaoto Horiguchi, S. Biesemans, Monique Ercken et al.|Unknown|2010Cited by 8