Benchmarking SOI and bulk FinFET alternatives for PLANAR CMOS scaling successionT. Chiarella, Thomas Hoffmann, Liesbeth Witters et al.|Solid-State Electronics|2010Cited by 120
Layout impact on the performance of a locally strained PMOSFETS. Eneman, S. Biesemans, Peter Verheyen et al.|Unknown|2005Cited by 44
25% drive current improvement for p-type multiple gate FET (MuGFET) devices by the introduction of recessed Si/sub 0.8/Ge/sub 0.2/ in the source and drain regions.Peter Verheyen, S. Biesemans, Nadine Collaert et al.|Unknown|2005Cited by 38
Gate-last vs. gate-first technology for aggressively scaled EOT logic/RF CMOSA. Veloso, Thomas Hoffmann, L.-Å. Ragnarsson et al.|Symposium on VLSI Technology|2011Cited by 31
Migrating from planar to FinFET for further CMOS scaling: SOI or bulk?T. Chiarella, Thomas Hoffmann, C. Ortolland et al.|Unknown|2009Cited by 27