Highly manufacturable FinFETs with sub-10nm fin width and high aspect ratio fabricated with immersion lithographyM.J.H. van Dal, R.J.P. Lander, Nadine Collaert et al.|Unknown|2007Cited by 79
Flexible and robust capping-metal gate integration technology enabling multiple-VT CMOS in MuGFETsA. Veloso, M. Jurczak, Liesbeth Witters et al.|Unknown|2008Cited by 27
Demonstration of recessed SiGe S/D and inserted metal gate on HfO/sub 2/ for high performance pFETs.Peter Verheyen, S. Biesemans, Geert Eneman et al.|Unknown|2006Cited by 20
Low V<inf>T</inf> CMOS using doped Hf-based oxides, TaC-based Metals and Laser-only AnnealS. Kubicek, S. Biesemans, T. Schram et al.|Unknown|2007Cited by 18
Demonstration of scaled 0.099&#x00B5;m<sup>2</sup> FinFET 6T-SRAM cell using full-field EUV lithography for (Sub-)22nm node single-patterning technologyA. Veloso, S. Biesemans, S. Demuynck et al.|Unknown|2009Cited by 14