Integration of tall triple-gate devices with inserted-Ta/sub x/N/sub y/ gate in a 0.274μm/sup 2/ 6t-sram cell and advanced CMOS logic circuits
Liesbeth Witters(IMEC), S. Biesemans(IMEC), J. Van Aelst(IMEC), David Laidler(IMEC), Patrick Willems(IMEC), Jean‐François de Marneffe(IMEC), Abhisek Dixit(IMEC), Werner Boullart(IMEC), Geert Vandenberghe(IMEC), S. Locorotondo(IMEC), M. Jurczak(IMEC), A. Lauwers(IMEC), S. Brus(University of Liège), Ivan Pollentier(IMEC), Vincent Wiaux(Imec the Netherlands), Myriam Moelants, Mireille Maenhoudt(IMEC), Nadine Collaert(IMEC), M. Demand(IMEC), C. Vrancken(IMEC), S. Vanhaelemeersch(Imec the Netherlands), Christie Delvaux(IMEC), Patrick Jaenen(IMEC), Eric Hendrickx(University of Arizona), Janko Versluijs(IMEC), Jan Wouters(KU Leuven), N. Heylen(IMEC), Kris Baert(Ghent University), A. Nackaerts(IMEC), S. Beckx(Imec the Netherlands), S. Demuynck(IMEC), Philippe Leray(IMEC), M. Goodwinc(IMEC), T. Vandeweyerd(IMEC), Monique Ercken(IMEC), B. Degroote(IMEC), R. Rooyackers(IMEC), Staf Verhaegen(IMEC), J. Van Olmen(IMEC), M. Van Hove(IMEC), K. De Meyer(IMEC), Kurt Ronse(IMEC)
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