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Vertical Nanowire and Nanosheet FETs: Device Features, Novel Schemes for Improved Process Control and Enhanced Mobility, Potential for Faster & More Energy Efficient CircuitsA. Veloso, Philippe Matagne, Geert Eneman et al.|Unknown|2019Cited by 41
Junctionless gate-all-around lateral and vertical nanowire FETs with simplified processing for advanced logic and analog/RF applications and scaled SRAM cellsA. Veloso, Aaron Thean, Bertrand Parvais et al.|Unknown|2016Cited by 37
Challenges and opportunities of vertical FET devices using 3D circuit design layoutsA. Veloso, Monique Ercken, W. Li et al.|Unknown|2016Cited by 17
Integration of tall triple-gate devices with inserted-Ta/sub x/N/sub y/ gate in a 0.274μm/sup 2/ 6t-sram cell and advanced CMOS logic circuitsLiesbeth Witters, S. Biesemans, K. De Meyer et al.|Unknown|2005Cited by 12