Integration of tall triple-gate devices with inserted-Ta/sub x/N/sub y/ gate in a 0.274μm/sup 2/ 6t-sram cell and advanced CMOS logic circuitsLiesbeth Witters, S. Biesemans, S. Beckx et al.|Unknown|2005Cited by 12
Integration of tall triple-gate devices with inserted TaxNy gate in a 0.274µm2 6T-SRAM cell and advanced CMOS logic circuitsLiesbeth Witters, S. Biesemans, Nadine Collaert et al.|Unknown|2005Cited by 4
Excellent stability of GaN-on-Si HEMTs with 5 µm gate-drain spacing tested in off-state at a record drain voltage of 200 V and 200℃Denis Marcon, G. Borghs, M. Van Hove et al.|Unknown|2009Cited by 0
Self-heating assesment of GaN DHFETs using mono-lithically fabricated 2-DEG resistorsPuneet Srivastava, Gustaaf Borghs, J. Das et al.|Unknown|2010Cited by 0