Integration of tall triple-gate devices with inserted-Ta/sub x/N/sub y/ gate in a 0.274μm/sup 2/ 6t-sram cell and advanced CMOS logic circuitsLiesbeth Witters, S. Biesemans, Nadine Collaert et al.|Unknown|2005Cited by 12
Implementation of high-k and metal gate materials for the 45nm node and beyond: gate patterning developmentS. Beckx, B. Coenegrachts, S. Biesemans et al.|Microelectronics Reliability|2005Cited by 12
Integration of tall triple-gate devices with inserted TaxNy gate in a 0.274µm2 6T-SRAM cell and advanced CMOS logic circuitsLiesbeth Witters, S. Biesemans, Nadine Collaert et al.|Unknown|2005Cited by 4
Influence of oxide hard mask on profiles of sub-100 nm Si and SiGe gatesDenis Shamiryan, S. Vanhaelemeersch, Vasile Paraschiv et al.|Journal of Vacuum Science & Technology B Microelectronics and Nanometer Structures Processing Measurement and Phenomena|2005Cited by 2
Effect Of Ion-bombardment Intensity Due To The Charging On Sidewall Trench FormatiomH.C. Lee, S. Vanhaelemeersch, S. Beckx|Unknown|1997Cited by 0