Gate-last vs. gate-first technology for aggressively scaled EOT logic/RF CMOS
A. Veloso(IMEC), Thomas Hoffmann(IMEC), T. Kauerauf(IMEC), M. J. Cho(IMEC), Hilde Tielens(IMEC), Farid Sebaai(IMEC), Samuel Suhard, M. Dehan, S. Brus(University of Liège), K. L. Pey(Singapore University of Technology and Design), Shinji Takeoka(Waseda University), Herbert Struyf(IMEC), Thierry Conard(IMEC), Vasile Paraschiv(IMEC), K. Devriendt(IMEC), A. Van Ammel, Paola Favia(IMEC), Alexis Franquet(IMEC), E. Röhr(IMEC), Y. Crabbe(IMEC), L.-Å. Ragnarsson(IMEC), Yuki Higuchi(Toyota Central Research and Development Laboratories (Japan)), Kristof Kellens(IMEC), Naoto Horiguchi(IMEC), H. Bender(IMEC), Geert Eneman(Research Foundation - Flanders), P. Absil(IMEC), Sun-Gi Hong(Samsung (South Korea)), X. Li(Agency for Science, Technology and Research), S. Yamaguchi, Paul Mertens(IMEC), T. Schram(IMEC)
Symposium on VLSI Technology
June 14, 2011
Cited by 31
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