6&#x00C5; EOT Si<inf>0.45</inf>Ge<inf>0.55</inf> pMOSFET with optimized reliability (V<inf>DD</inf>=1V): Meeting the NBTI lifetime target at ultra-thin EOT
J. Franco(KU Leuven), G. Groeseneken(KU Leuven), Shinji Takeoka(Waseda University), T. Kauerauf(IMEC), A. Stesmans(KU Leuven), Ph. Roussel(IMEC), W.-E. Wang(Intel (United States)), B. Kaczer(IMEC), Liesbeth Witters(IMEC), R. Degraeve(IMEC), Tibor Grasser(TU Wien), Geert Eneman(Research Foundation - Flanders), T. Y. Hoffmann(IMEC), M. Toledano-Luque(Universidad Complutense de Madrid), Lars‐Åke Ragnarsson(IMEC), Jérôme Mitard(IMEC), Joshua Tseng(IMEC), V. V. Afanas’ev(IMEC), M. Cho(IMEC)
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