Flexible and robust capping-metal gate integration technology enabling multiple-VT CMOS in MuGFETs
A. Veloso(IMEC), M. Jurczak(IMEC), Eddy Simoen(IMEC), Rita Vos(IMEC), S. Brus(University of Liège), T. Kauerauf(IMEC), Thierry Conard(IMEC), Nadine Collaert(IMEC), N.J. Son(IMEC), M. Demand(IMEC), Ph. Roussel(IMEC), B. Kaczer(IMEC), Isabelle Ferain(IMEC), Liesbeth Witters(IMEC), Christoph Adelmann(Imec the Netherlands), H. Bender(IMEC), Sven Van Elshocht(Columbia University), R. Rooyackers(IMEC), Olivier Richard(IMEC), K. De Meyer(IMEC), S. Biesemans(IMEC)
Cited by 27
Related Papers
New insights in the relation between electron trap generation and the statistical properties of oxide breakdown
|IEEE Transactions on Electron Devices|1998|647
Origin of the threshold voltage instability in SiO<sub>2</sub>/HfO<sub>2</sub> dual layer gate dielectrics
|IEEE Electron Device Letters|2003|360
Three-Dimensional Observation of the Conductive Filament in Nanoscaled Resistive Memory Devices
|Nano Letters|2014|338
Origin of NBTI variability in deeply scaled pFETs
|Unknown|2010|309