Highly manufacturable FinFETs with sub-10nm fin width and high aspect ratio fabricated with immersion lithographyM.J.H. van Dal, R.J.P. Lander, Andriy Hikavyy et al.|Unknown|2007Cited by 79
Gatestacks for scalable high-performance FinFETsG. Vellianitis, Liangzhen Lai, J. Pétry et al.|Unknown|2007Cited by 32
Scalability of Ni FUSI gate processes: phase and Vt control to 30 nm gate lenghtsJ. A. Kittl, S. Baesmans, A. Veloso et al.|Unknown|2005Cited by 28
CMOS Integration of Dual Work Function Phase-Controlled Ni Fully Silicided Gates (NMOS:NiSi, PMOS:$\hbox{Ni}_{2}\hbox{Si}$, and $\hbox{Ni}_{31}\hbox{Si}_{12}$) on HfSiONJ. A. Kittl, S. Biesemans, A. Lauwers et al.|IEEE Electron Device Letters|2006Cited by 21
CMOS integration of dual work function phase controlled Ni FUSI with simultaneous silicidation of NMOS (NiSi) and PMOS (Ni-rich silicide) gates on HfSiONA. Lauwers, J. A. Kittl, A. Veloso et al.|Unknown|2006Cited by 17