Nitride Engineering for Improved Erase Performance and Retention of TANOS NAND Flash Memory
G. Van den bosch(IMEC), Jan Van Houdt(KU Leuven), Udayan Ganguly(Applied Materials (United States)), A. Furnémont(IMEC), A. Rothschild(IMEC), Chris Olsen(Applied Materials (United States)), M. B. Zahid(IMEC), A. Cacciato(IMEC), L. Breuil(IMEC), R. Degraeve(IMEC)
Cited by 31
Related Papers
Ultrathin (<4 nm) SiO2 and Si–O–N gate dielectric layers for silicon microelectronics: Understanding the processing, structure, and physical and electrical limits
|Journal of Applied Physics|2001|772
New insights in the relation between electron trap generation and the statistical properties of oxide breakdown
|IEEE Transactions on Electron Devices|1998|647
Origin of the threshold voltage instability in SiO<sub>2</sub>/HfO<sub>2</sub> dual layer gate dielectrics
|IEEE Electron Device Letters|2003|360