Characterization of the V/sub T/-instability in SiO/sub 2//HfO/sub 2/ gate dielectrics
A. Kerber(Infineon Technologies (Germany)), Udo Schwalke(Technische Universität Darmstadt), M. Rosmeulen(IMEC), L. Pantisano(IMEC), R. Degraeve(IMEC), E. Cartier(IBM (United States)), T. Kauerauf(IMEC), H.E. Maes(IMEC), G. Groeseneken(KU Leuven)
Cited by 92
Related Papers
Ultrathin (<4 nm) SiO2 and Si–O–N gate dielectric layers for silicon microelectronics: Understanding the processing, structure, and physical and electrical limits
|Journal of Applied Physics|2001|772
New insights in the relation between electron trap generation and the statistical properties of oxide breakdown
|IEEE Transactions on Electron Devices|1998|647
Origin of the threshold voltage instability in SiO<sub>2</sub>/HfO<sub>2</sub> dual layer gate dielectrics
|IEEE Electron Device Letters|2003|360