A record Gm<sub>SAT</sub>/SS<sub>SAT</sub> and PBTI reliability in Si-passivated Ge nFinFETs by improved gate stack surface preparationHiroaki Arimura, Naoto Horiguchi, Liesbeth Witters et al.|Unknown|2019Cited by 12
Ge oxide scavenging and gate stack nitridation for strained Si<sub>0.7</sub>Ge<sub>0.3</sub> pFinFETs enabling 35% higher mobility than SiHiroaki Arimura, Naoto Horiguchi, Kurt Wostyn et al.|Unknown|2019Cited by 10
Addressing Key Challenges for SiGe-pFin Technologies: Fin Integrity, Low-DIT Si-Cap-Free Gate Stack and Optimizing the Channel StrainHiroaki Arimura, Naoto Horiguchi, E. Capogreco et al.|Unknown|2020Cited by 8
Challenges and Opportunities for Vertical Nanowire FETs: Device Design and FabricationA. Veloso, Julien Ryckaert, Philippe Matagne et al.|Extended Abstracts of the 2018 International Conference on Solid State Devices and Materials|2018Cited by 3