Dipole-First Gate Stack as a Scalable and Thermal Budget Flexible Multi-Vt Solution for Nanosheet/CFET DevicesHiroaki Arimura, Naoto Horiguchi, Lars‐Åke Ragnarsson et al.|Unknown|2021Cited by 29
BTI Reliability Improvement Strategies in Low Thermal Budget Gate Stacks for 3D Sequential IntegrationJ. Franco, B. Kaczer, Zhicheng Wu et al.|Unknown|2018Cited by 24
V<sub>t</sub> Fine-Tuning in Multi-V<sub>t</sub> Gate-All-Around Nanosheet nFETs Using Rare-Earth Oxide-Based Dipole-First Gate Stack Compatible with CFET IntegrationHiroaki Arimura, Naoto Horiguchi, T. Chiarella et al.|Unknown|2024Cited by 16
A record Gm<sub>SAT</sub>/SS<sub>SAT</sub> and PBTI reliability in Si-passivated Ge nFinFETs by improved gate stack surface preparationHiroaki Arimura, Naoto Horiguchi, Daire Cott et al.|Unknown|2019Cited by 12
FinFETs with Thermally Stable RMG Gate Stack for Future DRAM Peripheral CircuitsE. Capogreco, Naoto Horiguchi, Hiroaki Arimura et al.|2022 International Electron Devices Meeting (IEDM)|2022Cited by 10