Charge trapping and dielectric reliability of SiO/sub 2/-Al/sub 2/O/sub 3/ gate stacks with TiN electrodes
A. Kerber(Infineon Technologies (Germany)), Udo Schwalke(Technische Universität Darmstadt), L. Pantisano(IMEC), Ph. Roussel(IMEC), R. Degraeve(IMEC), E. Cartier(IBM (United States)), T. Kauerauf(IMEC), H.E. Maes(IMEC), G. Groeseneken(KU Leuven)
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