(Invited) Vertical Nanowire FET Integration and Device AspectsA. Veloso, Aaron Thean, Zheng Tao et al.|ECS Transactions|2016Cited by 50
Junctionless gate-all-around lateral and vertical nanowire FETs with simplified processing for advanced logic and analog/RF applications and scaled SRAM cellsA. Veloso, Aaron Thean, Bertrand Parvais et al.|Unknown|2016Cited by 37
Challenges and opportunities of vertical FET devices using 3D circuit design layoutsA. Veloso, Monique Ercken, W. Li et al.|Unknown|2016Cited by 17
Vertical nanowire FET integration and device aspectsA. Veloso, Aaron Thean, Efrain Altamirano Sánchez et al.|Unknown|2016Cited by 14
(Invited) Challenges on Surface Conditioning in 3D Device Architectures: Triple-Gate FinFETs, Gate-All-Around Lateral and Vertical Nanowire FETsA. Veloso, Nadine Collaert, Vasile Paraschiv et al.|ECS Transactions|2017Cited by 8