Record I<inf>ON</inf>/I<inf>OFF</inf> performance for 65nm Ge pMOSFET and novel Si passivation scheme for improved EOT scalabilityJérôme Mitard, Marc Heyns, Brice De Jaeger et al.|Unknown|2008Cited by 56
25% drive current improvement for p-type multiple gate FET (MuGFET) devices by the introduction of recessed Si/sub 0.8/Ge/sub 0.2/ in the source and drain regions.Peter Verheyen, S. Biesemans, Nadine Collaert et al.|Unknown|2005Cited by 38
Diffusion of solvents in thin porous filmsDenis Shamiryan, Karen Maex, Mikhaı̈l R. Baklanov et al.|Colloids and Surfaces A Physicochemical and Engineering Aspects|2006Cited by 29
Demonstration of recessed SiGe S/D and inserted metal gate on HfO/sub 2/ for high performance pFETs.Peter Verheyen, S. Biesemans, Geert Eneman et al.|Unknown|2006Cited by 20
Implementation of high-k and metal gate materials for the 45nm node and beyond: gate patterning developmentS. Beckx, B. Coenegrachts, M. Demand et al.|Microelectronics Reliability|2005Cited by 12