Investigation of poly-Si/HfO/sub 2/ gate stacks in a self-aligned 70nm MOS process flow
S. Kubicek(IMEC), K. De Meyer(IMEC), R.J. Carter(IMEC), L. Pantisano(IMEC), Matty Caymax(IMEC), Marc Heyns(IMEC), Patrick Jaenen(IMEC), Werner Boullart(IMEC), J. Chen(IMEC), E. Cartier(IMEC), S. Beckx(Imec the Netherlands), A. Kerber(Infineon Technologies (Germany)), Lars‐Åke Ragnarsson(IMEC), S. DeGendt(IMEC), V. Kaushik(IMEC), G.S. Lujan(IMEC), W.K. Henson(IMEC)
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