Integration of high-k gate dielectrics - Wet etch, cleaning and surface conditioning
Stefan De Gendt(Imec the Netherlands), Marc Heyns(IMEC), W. Deweerd(IMEC), Annelies Delabie(IMEC), David Hellin, T. Witters(IMEC), Bart Onsia, Thierry Conard(IMEC), Matty Caymax(IMEC), E. Röhr(IMEC), Harald Kraus, V. Parashiv, Patrick Van Doorne(IMEC), Martine Claes(Imec the Netherlands), S. Beckx(Imec the Netherlands), Sven Van Elshocht(Columbia University), W.C. Tsai, Riikka L. Puurunen(Aalto University), James Snow(IMEC), Johan Vertommen(Lam Research (Austria))
Unknown
January 1, 2004
Cited by 0
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