Achieving Low-$V_{T}$ Ni-FUSI CMOS by Ultra-Thin $\hbox{Dy}_{2}\hbox{O}_{3}$ Capping of Hafnium Silicate Dielectrics
A. Veloso(IMEC), S. Biesemans(IMEC), A. Lauwers(IMEC), Bart Onsia, S. Brus(University of Liège), M. Demand(IMEC), Christoph Adelmann(Imec the Netherlands), H.Y. Yu(IMEC), Geoffrey Pourtois(IMEC), P. Lehnen(IMEC), Barry O’Sullivan(Toshiba (Japan)), P. Absil(IMEC), Sven Van Elshocht(Columbia University), R. Singanamalla(IMEC), S.Z. Chang(KU Leuven), K. De Meyer(IMEC), M. Jurczak(IMEC)
Cited by 0
Related Papers
Three-Dimensional Observation of the Conductive Filament in Nanoscaled Resistive Memory Devices
|Nano Letters|2014|338
Effective electrical passivation of Ge(100) for high-k gate dielectric layers using germanium oxide
|Applied Physics Letters|2007|271
Germanium MOSFET Devices: Advances in Materials Understanding, Process Development, and Electrical Performance
|Journal of The Electrochemical Society|2008|267
Endurance/Retention Trade-off on $\hbox{HfO}_{2}/\hbox{Metal}$ Cap 1T1R Bipolar RRAM
|IEEE Transactions on Electron Devices|2013|259