Investigation of temperature acceleration of thin oxide time-to-breakdown

B. Kaczer(IMEC), G. Groeseneken(KU Leuven), T. Nigam(IMEC), R. Degraeve(IMEC), N. Pangon(IMEC)
Microelectronic Engineering
September 1, 1999
10.1016/s0167-9317(99)00335-4
Cited by 29

Related Papers

Ultrathin (<4 nm) SiO2 and Si–O–N gate dielectric layers for silicon microelectronics: Understanding the processing, structure, and physical and electrical limits
|Journal of Applied Physics|2001|772
New insights in the relation between electron trap generation and the statistical properties of oxide breakdown
|IEEE Transactions on Electron Devices|1998|647
10×10nm<sup>2</sup> Hf/HfO<inf>x</inf> crossbar resistive RAM with excellent performance, reliability and low-energy operation
|Unknown|2011|611
Origin of the threshold voltage instability in SiO<sub>2</sub>/HfO<sub>2</sub> dual layer gate dielectrics
|IEEE Electron Device Letters|2003|360
A consistent model for the thickness dependence of intrinsic breakdown in ultra-thin oxides
|Unknown|2002|337