Optimization of Structure and Electrical Characteristics for Four-Layer Vertically-Stacked Horizontal Gate-All-Around Si Nanosheets Devices
Qingzhu Zhang(Hebei University of Technology), Jun Luo(Fujian Medical University), Xiaobin He(Chinese Academy of Sciences), Renren Xu(Chinese Academy of Sciences), Huaxiang Yin(Chinese Academy of Sciences), Zhenhua Wu(Zhejiang University), Henry H. Radamson(Chinese Academy of Sciences), Jiaxin Yao(Chinese Academy of Sciences), Hong Yang(Chinese Academy of Sciences), Zhenzhen Kong(Institute of Microelectronics), Zhaohao Zhang(Chinese Academy of Sciences), Gaobo Xu(University of Chinese Academy of Sciences), Guilei Wang(Beijing Academy of Science and Technology), Jie Gu(Chinese Academy of Sciences), Junjie Li(University of Chinese Academy of Sciences), Jinjuan Xiang(University of Chinese Academy of Sciences), Lei Cao(University of Science and Technology Liaoning), Jiajia Tian(Zhengzhou University), Shujuan Mao(Chinese Academy of Sciences)
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