BJT-Mode Endurance on a 1T-RAM Bulk FinFET Device
M. Aoulaiche(IMEC), L. Altimime(IMEC), Zhichao Lu(University of Florida), Nadine Collaert(IMEC), R. Degraeve(IMEC), G. Groeseneken(KU Leuven), Bart De Wachter(IMEC), M. Jurczak(IMEC)
Cited by 19
Related Papers
Ultrathin (<4 nm) SiO2 and Si–O–N gate dielectric layers for silicon microelectronics: Understanding the processing, structure, and physical and electrical limits
|Journal of Applied Physics|2001|772
New insights in the relation between electron trap generation and the statistical properties of oxide breakdown
|IEEE Transactions on Electron Devices|1998|647
Origin of the threshold voltage instability in SiO<sub>2</sub>/HfO<sub>2</sub> dual layer gate dielectrics
|IEEE Electron Device Letters|2003|360