Hole trapping and trap generation in the gate silicon dioxide

J. F. Zhang(Liverpool John Moores University), R. Degraeve(IMEC), G. Groeseneken(KU Leuven), H.K. Sii(Liverpool John Moores University)
IEEE Transactions on Electron Devices
June 1, 2001
10.1109/16.925238
Cited by 68

Related Papers

Ultrathin (<4 nm) SiO2 and Si–O–N gate dielectric layers for silicon microelectronics: Understanding the processing, structure, and physical and electrical limits
|Journal of Applied Physics|2001|772
New insights in the relation between electron trap generation and the statistical properties of oxide breakdown
|IEEE Transactions on Electron Devices|1998|647
10×10nm<sup>2</sup> Hf/HfO<inf>x</inf> crossbar resistive RAM with excellent performance, reliability and low-energy operation
|Unknown|2011|611
Origin of the threshold voltage instability in SiO<sub>2</sub>/HfO<sub>2</sub> dual layer gate dielectrics
|IEEE Electron Device Letters|2003|360
A consistent model for the thickness dependence of intrinsic breakdown in ultra-thin oxides
|Unknown|2002|337