Layout impact on the performance of a locally strained PMOSFET
S. Eneman(Fund for Scientific Research), S. Biesemans(IMEC), Victor Moroz(V.A. Negovsky Scientific Research Institute of General Reanimatology), R. Schreutelkamp(Applied Materials (United States)), L. Washington(Applied Materials (United States)), A. De Keersgieter(IMEC), B. Kaczer(IMEC), R. Degraeve(IMEC), Y. Kim(Applied Materials (United States)), Peter Verheyen(IMEC), P. Absil(IMEC), Lee Smith(Synopsys (United States)), F. Nouri(Applied Materials (United States)), Mayuka F. Kawaguchi(Applied Materials (United States)), R. Rooyackers(IMEC), Arkadii V. Samoilov(Applied Materials (United States)), K. De Meyer(IMEC), M. Jurczak(IMEC)
Cited by 44
Related Papers
Ultrathin (<4 nm) SiO2 and Si–O–N gate dielectric layers for silicon microelectronics: Understanding the processing, structure, and physical and electrical limits
|Journal of Applied Physics|2001|772
New insights in the relation between electron trap generation and the statistical properties of oxide breakdown
|IEEE Transactions on Electron Devices|1998|647
Origin of the threshold voltage instability in SiO<sub>2</sub>/HfO<sub>2</sub> dual layer gate dielectrics
|IEEE Electron Device Letters|2003|360