Complementary silicide source/drain thin-body MOSFETs for the 20 nm gate length regimeJ. Kedzierski, Chenming Hu, Jeffrey Bokor et al.|Unknown|2002Cited by 214
A spacer patterning technology for nanoscale CMOSYang‐Kyu Choi, Chenming Hu, Tsu-Jae King|IEEE Transactions on Electron Devices|2002Cited by 207
Transistor characteristics with Ta/sub 2/O/sub 5/ gate dielectricDonggun Park, Chia-Cheng Cheng, A. Kalnitsky et al.|IEEE Electron Device Letters|1998Cited by 102
Leakage current comparison between ultra-thin Ta<sub>2</sub>O<sub>5</sub> films and conventional gate dielectricsQiang Lu, Chenming Hu, Tsu-Jae King et al.|IEEE Electron Device Letters|1998Cited by 72
Impact of time dependent dielectric breakdown and stress-induced leakage current on the reliability of high dielectric constant (Ba,Sr)TiO/sub 3/ thin-film capacitors for Gbit-scale DRAMsShintaro Yamamichi, Chenming Hu, Akiko Yamamichi et al.|IEEE Transactions on Electron Devices|1999Cited by 29