A low-voltage biasing scheme for aggressively scaled bulk FinFET 1T-DRAM featuring 10s retention at 85°C
Nadine Collaert(IMEC), M. Jurczak(IMEC), M. Aoulaiche(IMEC), L. Altimime(IMEC), S. Brus(University of Liège), A. De Keersgieter(IMEC), Naoto Horiguchi(IMEC), Michał Rakowski(IMEC), B. De Wachter(IMEC), A. Redolfi(IMEC)
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