Junction optimization for Reliability issues in floating gate NAND flash cellsChieh-En Lee, Chih-Yuan Lu, I. J. Huang et al.|Unknown|2011Cited by 7
Highly Scalable and Reliable Multi-bit/cell Nitride Trapping Nonvolatile Memory Using Enhanced ANS-ONO Process with A Nitridized InterfaceYang‐Hsin Shih, Erh-Kun Lai, Jung-Yu Hsieh et al.|Unknown|2006Cited by 6
Program Trapped-Charge Effect on Random Telegraph-Noise Amplitude in a Planar SONOS Flash Memory CellH.C. Ma, Chih-Yuan Lu, You-Liang Chou et al.|IEEE Electron Device Letters|2009Cited by 5
Program charge effect on random telegraph noise amplitude and its device structural dependence in SONOS flash memoryJ.P. Chiu, Chih-Yuan Lu, You-Liang Chou et al.|Unknown|2009Cited by 3
Chip-level reliability study of barrier engineered (BE) floating gate (FG) Flash memory devicesHang-Ting Lue, Chih-Yuan Lu, JiFong Pan et al.|Unknown|2010Cited by 1