Design, Materials, Process, Fabrication, and Reliability of Fan-Out Wafer-Level PackagingJohn H. Lau, S. W. Ricky Lee, Yiu-Ming Cheung et al.|IEEE Transactions on Components Packaging and Manufacturing Technology|2018Cited by 96
Fan-Out Wafer-Level Packaging for Heterogeneous IntegrationJohn H. Lau, S. W. Ricky Lee, Ming Li et al.|IEEE Transactions on Components Packaging and Manufacturing Technology|2018Cited by 87
Warpage Measurements and Characterizations of Fan-Out Wafer-Level Packaging With Large Chips and Multiple Redistributed LayersJohn H. Lau, Xi Cao, Ming Li et al.|IEEE Transactions on Components Packaging and Manufacturing Technology|2018Cited by 51
Chip-First Fan-Out Panel-Level Packaging for Heterogeneous IntegrationCheng-Ta Ko, S. W. Ricky Lee, Kai-Ming Yang et al.|IEEE Transactions on Components Packaging and Manufacturing Technology|2018Cited by 49
Fan-Out Wafer-Level Packaging (FOWLP) of Large Chip with Multiple Redistribution Layers (RDLs)John H. Lau, S. W. Ricky Lee, Ming Li et al.|Journal of Microelectronics and Electronic Packaging|2017Cited by 40