Lingli Jiang

A Comprehensive Review of Recent Progress on GaN High Electron Mobility Transistors: Devices, Fabrication and Reliability

Fanming Zeng, Judy X. An, Guangnan Zhou et al.|Electronics|2018

Cited by 165Open Access

GaN based high electron mobility transistors (HEMTs) have demonstrated extraordinary features in the applications of high power and high frequency devices. In this paper, we review recent progress in AlGaN/GaN HEMTs, including the following sections. First, challenges in device fabrication and optimizations will be discussed. Then, the latest progress in device fabrication technologies will be presented. Finally, some promising device structures from simulation studies will be discussed.

Smart City, Smart Transportation: Recommendations of the Logistics Platform Construction

Lingli Jiang|Unknown|2015

Cited by 40

Smart transportation is one aspect of the smart city. Because the low efficiency, the transportation has became the second largest industry of carbon emissions. It's not only affect the smart transportation, but also affect the smart environment. So, improve the efficiency of the transportation is very important to the smart transportation and smart city. The logistics platform is a new business model, which can be improve the un-load rate and decrease the carbon emissions. But, the logistics platforms are at the early development. How to build is a very important issue. This paper has given three suggestions to it. Firstly, to clarify the roles what you will to be, secondly, to choose the model of the platform which fit for your company, thirdly, using an iterative development model to design the product.

Evaluation of LPCVD SiN<italic>x</italic> Gate Dielectric Reliability by TDDB Measurement in Si-Substrate-Based AlGaN/GaN MIS-HEMT

Yongle Qi, Yumeng Zhu, Jian Zhang et al.|IEEE Transactions on Electron Devices|2018

Cited by 35

Si-substrate-based AlGaN/GaN high-electron mobility power transistors with low pressure chemical vapor deposition (LPCVD) SiN x as gate isolation material are fabricated on a 6-in wafer by CMOS compatible process. The dielectric failure by forward-biased constant-voltage stress time-dependent dielectric breakdown (TDDB) measurements at various temperatures (from room temperature to 250 °C) and their statistical Weibull analysis are compared. Impact of gate dielectric area and multifinger on the SiN x TDDB characteristics is also discussed. Using thermal microscope imager, the leakage current spots have been identified. The mean time to failure decreases with the increasing finger numbers in exponential form. We also predict the device ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${W}_{G}= {0.25}$ </tex-math></inline-formula> mm) with 35-nm-thick LPCVD SiN x gate dielectric can survive at a positive gate voltage of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {GS}}= {15}$ </tex-math></inline-formula> V for a 10-year time-to-breakdown lifetime (100 ppm and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${T}= {25}$ </tex-math></inline-formula> °C) and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {GS}}= {7.5}$ </tex-math></inline-formula> V for a 10-year time-to-breakdown lifetime (100 ppm and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${T}= {250}$ </tex-math></inline-formula> °C).

A 0.35 &#x03BC;m 700 V BCD technology with self-isolated and non-isolated ultra-low specific on-resistance DB-nLDMOS

Kun Mao, Ming Qiao, Lingli Jiang et al.|Unknown|2013

Cited by 30

Integrated in a 0.35 μm 700 V BCD process platform, ultra-low R on, sp 700 V self-ISO (isolated) and NISO (non-isolated) DB-nLDMOS (dual P-buried-layer nLDMOS) are proposed in this paper. 800 V and 780 V are achieved for NISO and ISO DB-nLDMOS, of which R on, sp are 11.5 Ω·mm 2 and 11.2 Ω·mm 2 , respectively. Utra-low R on, sp benefits from optimized device size and strict limitations for annealing temperature and time after P-bury-layer implantation. For ISO DB-nLDMOS, by separately implanting NWELLs, NWELL drift region of low doping concentration under gate poly is achieved and then premature avalanche breakdown around bird's beak is avoided. Moreover, a 600 V DB-nJFET (dual P-buried-layer nJFET) with innovative 3D pinch-off structure is also presented.

High-voltage thick layer SOI technology for PDP scan driver IC

Ming Qiao, Lingli Jiang, Meng Wang et al.|Unknown|2011

Cited by 27

Based on 11-μm-thick silicon layer and 1-μm-thick buried oxide layer, a novel high-voltage thick layer SOI technology has been developed for driving plasma display panels (PDP). HV pLDMOS, nLDMOS, nLIGBT and LV CMOS are compatible with deep trench isolation. The length T, Y for HV pLDMOS and TD for HV nLDMOS are optimized to reduce the device size and satisfy the off-state breakdown voltage simultaneously. Interdigitated N + &P + and a deep P + are adopted in the source region of HV nLDMOS and cathode region of HV nLIGBT to suppress parasitic NPN action and gain better on-state characteristics. A PDP scan driver IC using the developed high-voltage thick layer SOI technology shows that the rise and fall times of the output stages are about 17.6 ns and 16.6 ns respectively.

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