High-voltage thick layer SOI technology for PDP scan driver IC

Ming Qiao(State Key Laboratory of Electronic Thin Films and Integrated Devices), Lingli Jiang(National Engineering Research Center of Electromagnetic Radiation Control Materials), Meng Wang(National Engineering Research Center of Electromagnetic Radiation Control Materials), Yong Huang(State Key Laboratory of Electronic Thin Films and Integrated Devices), Hong Liao(Changhong (China)), Tao Liang(State Key Laboratory of Electronic Thin Films and Integrated Devices), Zhen Sun(Changhong (China)), Bo Zhang(State Key Laboratory of Electronic Thin Films and Integrated Devices), Zhaoji Li(State Key Laboratory of Electronic Thin Films and Integrated Devices), Guangzuo Huang(Changhong (China)), Yuanyuan Zhao(State Key Laboratory of Electronic Thin Films and Integrated Devices), Li Lai(State Key Laboratory of Electronic Thin Films and Integrated Devices), Xi Hu(State Key Laboratory of Electronic Thin Films and Integrated Devices), Xiang Zhuang(State Key Laboratory of Electronic Thin Films and Integrated Devices), Xiaorong Luo(National Engineering Research Center of Electromagnetic Radiation Control Materials), Zhuo Wang(State Key Laboratory of Electronic Thin Films and Integrated Devices)
Unknown
May 1, 2011
10.1109/ispsd.2011.5890820
Cited by 27

Abstract

Based on 11-μm-thick silicon layer and 1-μm-thick buried oxide layer, a novel high-voltage thick layer SOI technology has been developed for driving plasma display panels (PDP). HV pLDMOS, nLDMOS, nLIGBT and LV CMOS are compatible with deep trench isolation. The length T, Y for HV pLDMOS and TD for HV nLDMOS are optimized to reduce the device size and satisfy the off-state breakdown voltage simultaneously. Interdigitated N <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> &P <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> and a deep P <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> are adopted in the source region of HV nLDMOS and cathode region of HV nLIGBT to suppress parasitic NPN action and gain better on-state characteristics. A PDP scan driver IC using the developed high-voltage thick layer SOI technology shows that the rise and fall times of the output stages are about 17.6 ns and 16.6 ns respectively.

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