A 0.35 μm 700 V BCD technology with self-isolated and non-isolated ultra-low specific on-resistance DB-nLDMOS

Kun Mao(University of Electronic Science and Technology of China), Ming Qiao(State Key Laboratory of Electronic Thin Films and Integrated Devices), Lingli Jiang(National Engineering Research Center of Electromagnetic Radiation Control Materials), Huaping Jiang(National Engineering Research Center of Electromagnetic Radiation Control Materials), Zehong Li(State Key Laboratory of Electronic Thin Films and Integrated Devices), Weizhong Chen(National Engineering Research Center of Electromagnetic Radiation Control Materials), Zhaoji Li(University of Electronic Science and Technology of China), Bo Zhang(University of Electronic Science and Technology of China)
Unknown
May 1, 2013
10.1109/ispsd.2013.6694429
Cited by 30

Abstract

Integrated in a 0.35 μm 700 V BCD process platform, ultra-low R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on, sp</sub> 700 V self-ISO (isolated) and NISO (non-isolated) DB-nLDMOS (dual P-buried-layer nLDMOS) are proposed in this paper. 800 V and 780 V are achieved for NISO and ISO DB-nLDMOS, of which R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on, sp</sub> are 11.5 Ω·mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and 11.2 Ω·mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , respectively. Utra-low R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on, sp</sub> benefits from optimized device size and strict limitations for annealing temperature and time after P-bury-layer implantation. For ISO DB-nLDMOS, by separately implanting NWELLs, NWELL drift region of low doping concentration under gate poly is achieved and then premature avalanche breakdown around bird's beak is avoided. Moreover, a 600 V DB-nJFET (dual P-buried-layer nJFET) with innovative 3D pinch-off structure is also presented.

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