Demonstration of scaled 0.099&#x00B5;m<sup>2</sup> FinFET 6T-SRAM cell using full-field EUV lithography for (Sub-)22nm node single-patterning technologyA. Veloso, S. Biesemans, E. Altamirano et al.|Unknown|2009Cited by 14
Full-field EUV and immersion lithography integration in 0.186&#x03BC;m<sup>2</sup> FinFET 6T-SRAM cellA. Veloso, Thomas Hoffmann, S. Demuynck et al.|Unknown|2008Cited by 9
Strain enhanced FUSI/HfSiON Technology with optimized CMOS Process WindowA. Veloso, S. Biesemans, Peter Verheyen et al.|Unknown|2007Cited by 2