A Leakage Management System Based on Clock Gating Infrastructure for a 65-nm Digital Base-Band Modem Chip
U. Ko(Texas Instruments (United States)), C. Raibaut(Texas Instruments (United States)), J. Ciroux(Texas Instruments (United States)), C. Fournet-Fayard(Texas Instruments (United States)), J.L. Lachese(Texas Instruments (United States)), O. Domerego(Texas Instruments (United States)), L. Bouetel(Texas Instruments (United States)), F. Ben-Amar(Texas Instruments (United States)), Michael Ball(Texas Instruments (United States)), J. Rosal(Texas Instruments (United States)), N. Culp(Texas Instruments (United States)), F. Piacibello(Texas Instruments (United States)), J. Vaccani(Texas Instruments (United States)), R. Hollingsworth(Texas Instruments (United States)), Vinod Menezes(Texas Instruments (United States)), M.A. Clinton(Texas Instruments (United States)), S. J. Thiruvengadam(Texas Instruments (United States)), Sumanth Gururajarao(Texas Instruments (United States)), Minh Quang Chau(Texas Instruments (United States)), Rolf Lagerquist(Texas Instruments (United States)), A. Er Rachidi(Texas Instruments (United States)), D.B. Scott(Texas Instruments (United States)), H. Mair(Texas Instruments (United States)), Philippe Royannez(Texas Instruments (United States)), F. Jumel(Texas Instruments (United States))
Cited by 10
Abstract
In this paper we present a leakage management system which takes advantage of the existing clock gating infrastructure. This methodology avoids both RTL and software changes, at the block and chip level. We illustrate this approach with a 65-nm digital base band modem while achieving standby leakage in the 100-muA range and overall 1200times leakage reduction including process, circuit and system optimization