90nm low leakage SoC design techniques for wireless applications

Philippe Royannez(Texas Instruments (United States)), H. Mair(Texas Instruments (United States)), Franck Dahan(Texas Instruments (United States)), M. Wagner(Texas Instruments (United States)), M. Streeter(Texas Instruments (United States)), L. Bouetel(Texas Instruments (United States)), J. Blasquez(Texas Instruments (France)), H. Clasen(Texas Instruments (United States)), G. Semino(Texas Instruments (France)), Julie Dong(Texas Instruments (France)), D.B. Scott(Texas Instruments (United States)), B. Pitts(Texas Instruments (France)), C. Raibaut(Texas Instruments (France)), Uming Ko(Texas Instruments (United States))
Unknown
August 30, 2005
10.1109/isscc.2005.1493907
Cited by 100

Abstract

The new generation of multimedia-application processors requires a drastic leakage reduction to bring the standby current to 50/spl mu/A. An efficient set of leakage reduction techniques, including power gating, memory retention, voltage scaling, and dual V/sub t/, is employed on a 50M transistor, 80mm/sup 2/ IC, fabricated in a 90nm CMOS technology, resulting in a 40/spl times/ leakage reduction.

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