Vinod Menezes

The full-wave rectifier is the most straightforward way of extracting energy from a piezoelectric source. Unfortunately, the inherent capacitance of the piezoelement significantly limits the efficiency of extraction. The bias-flip rectifier, which aims to mitigate this problem, not only needs a large inductor for efficient operation, but also needs the generation of pulses with a precisely defined ontime. A large inductor increases the overall volume of the system. We present the multi-stage bias-flip rectifier, which is a technique that achieves a high voltage-flip efficiency using a much smaller inductor, and relaxes timing-accuracy requirements. The rectifier, implemented in a 130-nm CMOS process, dissipates about 2 μW and achieves a voltage-flip efficiency of 89.5% while using only a 47 μH inductor.

With the Internet of Things (IoT) becoming ubiquitous, there is an ever-increasing demand for lowering power dissipation, especially for sensor nodes, where low energy consumption translates to longer battery life or operation with a smaller/cheaper battery. At the heart of a sensor node is a microcontroller running code from an embedded non-volatile memory (NVM). In order to support increasing computational needs and low latency (the ability to respond quickly to an event), the microcontroller needs to run at high performance (8–16MHz) and still have low power dissipation. Since most of sensor-node applications are event driven, the nodes, when not active, go into standby mode, to reduce power dissipation. In order to minimize the total energy consumption, it is important to not only reduce active-mode power, but to also lower the power consumption in standby mode, and have the ability to switch between the modes with low latency and low transition energy. Multiple low-power microcontroller implementations have been discussed in literature. Some, such as [1,2,3], aggressively address active mode power, but have higher standby mode power and also do not support CPU state retention. Other approaches [4,5], aggressively address the standby mode power, but have higher active-mode power, especially for code running from non-volatile memory. In this paper, we present an ultra-low-power microcontroller which addresses both active as well as standby-mode power reduction, and hence results in significantly lower total energy over a wide range of active-mode to standby-mode ratios ("duty cycle").

Voltage scaling is one of the knobs that is used today to control both static and the active power for SoCs. The SoC core supply voltage is scaled adaptively based on the performance needs. But it is also required to maintain the external electrical chip interface protocol, which may run at a different voltage level. The chip interfaces need to operate reliably under adaptively scaling core voltage and fixed 10 supply voltage. Within the 10 circuits, voltage level shifters are used to communicate between two voltage domains. This paper examines the performance of a conventional voltage level shifter and describes a novel high performance level shifter that is more robust under adapting voltage scaling.

We introduce the cyclic switched-capacitor dc-dc converter for single-input multiple-output power delivery. We focus on applications in stacked voltage domain (SVD)-based systems, and show that the cyclic architecture is robust to load current mismatches. We analyze such converters and give intuition for their power losses. We give experimental results from an SVD based power management integrated circuit (PMIC), designed and fabricated in a 130 nm CMOS technology. The PMIC is a combination of a 2/3 stage reconfigurable cyclic SC dc-dc converter and a linear regulator. It can drive 3×3 mA loads with the input supply voltage varying from 2.35-3.65 V.

In this paper we present a leakage management system which takes advantage of the existing clock gating infrastructure. This methodology avoids both RTL and software changes, at the block and chip level. We illustrate this approach with a 65-nm digital base band modem while achieving standby leakage in the 100-muA range and overall 1200times leakage reduction including process, circuit and system optimization