A logic-based embedded DRAM with novel cell structure and dynamically adaptive refresh for long data retention, zero data availability penalty and high yield
Xiaoyong Xue(Beijing University of Chinese Medicine), Jin Wu(Rambus (United States)), Qingtian Zou(The University of Texas Southwestern Medical Center), Chao Meng(Fudan University), Bin Chen(Zunyi Medical University), Rongjin Huang(Semiconductor Manufacturing International (China)), Yandan Lin, Chunling Dong(Second Affiliated Hospital of Jilin University)
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