First monolithic integration of Ge P-FETs and InAs N-FETs on silicon substrate: Sub-120 nm III-V buffer, sub-5 nm ultra-thin body, common raised S/D, and gate stack modulesSachin Yadav, Yee‐Chia Yeo, Nanyan Chen et al.|Unknown|2015Cited by 15
Gate-All-Around In<sub>0.53</sub>Ga<sub>0.47</sub>As Junctionless Nanowire FET With Tapered Source/Drain StructureKian-Hui Goh, Yee‐Chia Yeo, Sachin Yadav et al.|IEEE Transactions on Electron Devices|2016Cited by 14
(Invited) Enabling Hetero-Integration of III-V and Ge-Based Transistors on Silicon with Ultra-Thin Buffers Formed by Interfacial Misfit TechniqueXiao Gong, Yee‐Chia Yeo, Gengchiau Liang et al.|ECS Meeting Abstracts|2016Cited by 0