Computational Modeling and Validation of the Encapsulation of Plastic Packages by Transfer MoldingLuu Nguyen, C. Quentin, W. Lee et al.|Journal of Electronic Packaging|1999 This paper presents, discusses, and compares results from experimental and computational studies of the plastic encapsulation process for a 144-lead TQFP package. The experimental results were obtained using an instrumented molding press, while the computational predictions were obtained using a newly-developed software for modeling transfer molding processes. Validation of the software is emphasized, and this was done mainly by comparing the computational results with the corresponding experimental measurements for pressure, temperature, and flow front advancement in the cavities and runners. The experimental and computational results were found to be in good agreement, especially for the flow-front shapes and locations. [S1043-7398(00)00502-8]
A self-timed method to minimize spurious transitions in low power CMOS circuitsSpurious transitions and associated power are inherent disadvantages of a static logic design. Though pre-charged dynamic logic has the advantage of one valid transition per clock cycle, it has a considerable power overhead . In this paper, a low power self-timed double pass-gate logic (DPL) circuit combining the merits of dynamic and static logic families is proposed to minimize power in a 32-bit carry look-ahead static adder. This technique can be applied to any static circuit implementation, at any level of design hierarchy where power and performance are important. For a 100 MHz, 32-bit adder implementation in a 0.6 /spl mu/m CMOS technology results on output spurious transition density, total power dissipation and energy efficiency for different loads are presented.
A 62Gb/s backplane interconnect ASIC based on 3.1Gb/s serial-link technologyP. Landman, Ah-Lyan Yee, Runqi Gu et al.|2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)|2003 A backplane interconnect ASIC with 62 Gb/s full-duplex aggregate throughput uses 3.1 Gb/s serial link technology organized as 20 bidirectional channels to realize bandwidth. The chip operates with <5/spl times/10/sup 17/ aggregate BER and is fabricated in a 0.18 /spl mu/m CMOS technology, dissipating 9 W in a 768-pin flipchip BGA package.
Energy-dispersive, x-ray reflectivity density measurements of porous SiO2 xerogelsDonald Windover, Toh‐Ming Lu, S. L. Lee et al.|Applied Physics Letters|2000 X-ray reflectivity has been used to measure nondestructively the density of thin, porous, silica xerogels used for interlayer dielectric applications. The critical angle, defined through total external reflection, was measured for multiple x-ray energies to correct for sample misalignment error in the determination of the density for the films. This density was used to extrapolate the percentage porosity, assuming a bulk SiO2 density standard. The results were compared to those obtained by Rutherford backscattering and ellipsometry techniques.
A transmit architecture with 4-tap feedforward equalization for 6.25/12.5Gb/s serial backplane communicationsA transmit architecture with a programmable 4-tap feedforward equalizer for 6.25 to 12.5 Gb/s serial communications through lossy channels is described. A 16:8-channel MUX/DEMUX chip fabricated in a 0.13 /spl mu/m 7M CMOS process demonstrates a near-end jitter of 16 ps and an equalized far-end jitter of 55 ps at 6.25 Gb/s over a 36'' legacy backplane channel.