A 62Gb/s backplane interconnect ASIC based on 3.1Gb/s serial-link technology
P. Landman(Texas Instruments (United States)), Ah-Lyan Yee(Texas Instruments (United States)), Runqi Gu(Texas Instruments (United States)), B. Parthasarathy(Texas Instruments (United States)), Vijil Gupta(Texas Instruments (United States)), S. Ramaswamy(Texas Instruments (United States)), L. Dyson(Texas Instruments (United States)), P. Bosshart(Texas Instruments (United States)), J. Reynolds(Texas Instruments (United States)), M. Frannhagen, P. Fremrot, Stefan Johansson, K. Lewis, W. Lee(Texas Instruments (United States))
2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)
June 25, 2003
Cited by 20
Abstract
A backplane interconnect ASIC with 62 Gb/s full-duplex aggregate throughput uses 3.1 Gb/s serial link technology organized as 20 bidirectional channels to realize bandwidth. The chip operates with <5/spl times/10/sup 17/ aggregate BER and is fabricated in a 0.18 /spl mu/m CMOS technology, dissipating 9 W in a 768-pin flipchip BGA package.
Related Papers
No related papers found
Powered by citation graph analysis