Vikas Gupta

We describe double-lap shear experiments on Sn3.0Ag0.5Cu solder alloy, from which fits to Anand's viscoplastic constitutive model, power-law creep model, and to time-hardening primary-secondary creep model are derived. Results of monotonic tests for strain rates ranging from 4.02E-6 to 2.40E-3 s <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sup> , and creep response at stress levels ranging from 19.5 to 45.6 MPa are reported. Both types of tests were conducted at temperatures of 25degC, 75degC , and 125degC. Following an earlier study where Anand model and time hardening creep parameters for Sn3.8Ag0.7Cu and Sn1.0Ag0.5Cu solder alloys were reported, here we report power law model parameters so as to enable a comparison between all three alloys. Primary creep in Sn3.0Ag0.5Cu solder alloy is shown to be significant and are considered in addition to secondary creep and monotonic behavior. Aging influence on behavior is also shown to be significant. On the basis of experimental data, the following four aspects are discussed: 1) difference between testing on bulk versus joint specimen; 2) consistency between the creep and monotonic behaviors; 3) comparison against behaviors of Sn1.0Ag0.5Cu and Sn3.8Ag0.7Cu alloys as well as aganist Sn40Pb, 62Sn36Pb2Ag and 96.5Sn3.5Ag alloys; and 4) comparison of Sn3.0Ag0.5Cu and Sn3.8Ag0.7Cu relative to their aging response.

Constitutive models for SnAgCu solder alloys are of great interest at the present. Commonly, constitutive models that have been successfully used in the past for Sn-Pb solders are used to describe the behavior of SnAgCu solder alloys. Two issues in the modeling of lead-free solders demand careful attention: 1) Lead-free solders show significantly different creep strain evolution with time, stress and temperature, and the assumption of evolution to steady state creep nearly instantaneously may not be valid in SnAgCu alloys and 2) Models derived from bulk sample test data may not be reliable when predicting deformation behavior at the solder interconnection level for lead-free solders due to the differences in the inherent microstructures at these different scales. In addition, the building of valid constitutive models from test data derived from tests on solder joints must de-convolute the effects of joint geometry and its influence on stress heterogeneity. Such issues have often received insufficient attention in prior constitutive modeling efforts. In this study all of the above issues are addressed in developing constitutive models of Sn3.8Ag0.7Cu and Sn1.0Ag0.5Cu solder alloys, which represent the extremes of Ag composition that have been mooted at the present time. The results of monotonic testing are reported for strain rates ranging from 4.02E-6 to 2.40E-3 s <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sup> . The creep behavior at stress levels ranging from 7.8 to 52 MPa is also described. Both types of tests were performed at temperatures of 25degC, 75degC and 125degC. The popular Anand model and the classical time-hardening creep model are fit to the data, and the experimentally obtained model parameters are reported. The test data are compared against other reported data in the literature and conclusions are drawn on the plausible sources of error in the data reported in the prior literature.

A transceiver capable of 6.25-Gb/s data transmission across legacy communications equipment backplanes is described. To achieve a bit error rate (BER) <10/sup -15/, transmit and receive equalization that can compensate up to 20 dB of channel loss is employed to remove intersymbol interference (ISI) resulting from finite channel bandwidth and reflections. The transmit feed-forward equalizer (FFE) uses a four-tap symbol-spaced programmable finite impulse response (FIR) filter followed by a 4-bit digital-to-analog converter (DAC) that drives a 50-/spl Omega/ transmission line. The receiver uses a half-baud-rate adaptive decision feedback equalizer (DFE) that cancels the first four symbol-spaced taps of postcursor ISI without use of speculative techniques. Both the transmitter and receiver use an LC-oscillator-based phase-locked loop (PLL) to provide low jitter clocks. Techniques to minimize the complexity of the FIR and DFE implementations are described. The transceiver is designed to be integrated in a standard ASIC flow in a 0.13-/spl mu/m digital CMOS technology. System measurements indicate the ability to transmit and recover data eyes that have been fully closed due to crosstalk and signal loss.

The use of a substrate pump to achieve uniform npn protection in a multi-finger NMOS is reported for advanced CMOS technologies with silicide. The novel feature of this device technique is the implementation of a floating guardring to effectively pump the local substrate of the protection NMOS. SPICE simulations are presented to illustrate the device concept as well as the device design optimization.