A self-timed method to minimize spurious transitions in low power CMOS circuits

Abstract

Spurious transitions and associated power are inherent disadvantages of a static logic design. Though pre-charged dynamic logic has the advantage of one valid transition per clock cycle, it has a considerable power overhead . In this paper, a low power self-timed double pass-gate logic (DPL) circuit combining the merits of dynamic and static logic families is proposed to minimize power in a 32-bit carry look-ahead static adder. This technique can be applied to any static circuit implementation, at any level of design hierarchy where power and performance are important. For a 100 MHz, 32-bit adder implementation in a 0.6 /spl mu/m CMOS technology results on output spurious transition density, total power dissipation and energy efficiency for different loads are presented.