Sundeep Javvaji

The full-wave rectifier is the most straightforward way of extracting energy from a piezoelectric source. Unfortunately, the inherent capacitance of the piezoelement significantly limits the efficiency of extraction. The bias-flip rectifier, which aims to mitigate this problem, not only needs a large inductor for efficient operation, but also needs the generation of pulses with a precisely defined ontime. A large inductor increases the overall volume of the system. We present the multi-stage bias-flip rectifier, which is a technique that achieves a high voltage-flip efficiency using a much smaller inductor, and relaxes timing-accuracy requirements. The rectifier, implemented in a 130-nm CMOS process, dissipates about 2 μW and achieves a voltage-flip efficiency of 89.5% while using only a 47 μH inductor.

Bias-flip rectifiers are commonly employed for piezoelectric energy harvesting (PEH). This article proposes a synchronized switch harvesting on an inductor (SSHI) rectifier with a duty-cycle-based (DCB) maximum power point tracking (MPPT) algorithm. The proposed DCB MPPT algorithm is based on the mathematically derived relation between the MPPT efficiency and the duty cycle of the bridge rectifier. The resulting equation shows that the MPPT efficiency only depends on the rectifier duty cycle, and is independent of any other system variables, such as voltage bias-flipping efficiency, the open-circuit voltage from the harvester, vibration frequency, etc. As a result, MPPT can be achieved by regulating the duty cycle, simplifying circuit implementation, and achieving self-regulating and continuous MPPT. This design was fabricated in a 180-nm BCD process. The measured results show 98% peak MPPT efficiency and up to 738% output power enhancement.

Synchronized bias-flip rectifiers, such as synchronized switch harvesting on inductor (SSHI) rectifiers, are widely used for piezoelectric energy harvesting (PEH) [1], which can replace the use of batteries in many loT applications, thus reducing both system volume and maintenance cost. However, the output power extracted by such rectifiers strongly depends on the impedance matching between the piezoelectric transducer (PT) and the circuit. To maximize this, two maximum power point tracking (MPPT) algorithms are often used. As shown in Fig. 30.3.1 (left), the Perturb & Observe (P&O) (a.k.a. hill-climbing) algorithm adjusts the rectified output power in a stepwise manner towards the maximum power point (MPP), thus establishing robust and continuous MPPT. However, accurately sensing the rectified output power often requires complex and power-hungry hardware [1], [2]. Another simpler algorithm is based on the fractional open-circuit voltage (FOCV) and involves periodically measuring the PT's open-circuit voltage amplitude <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(\mathrm{V}_{\text{OC}})$</tex> and regulating the rectified voltage <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(\mathrm{V}_{\text{REC}})$</tex> to a level <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(\mathrm{V}_{\text{MPP}})$</tex> , which corresponds to the MPP [3–6]. However, the PT must be periodically disconnected from the rectifier to measure <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{V}_{\text{OC}}$</tex> , resulting in wasted energy, while the inherent delay in sensing <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{V}_{\text{OC}}$</tex> variations reduces the overall tracking efficiency. Furthermore, a calibration step is usually necessary to determine <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{V}_{\text{MPP}}$</tex> , since this depends on the actual PT voltage flip efficiency <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(\eta_{\mathrm{F}})$</tex> of the bias-flip rectifier.

Advances in CMOS technologies and circuit techniques have led to the development of continuous-time delta–sigma modulators (CT <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Delta \Sigma $ </tex-math></inline-formula> Ms) that sample at gigahertz (GHz) frequencies and achieve high linearity [−100 dBc and >120 dBFS spurious-free dynamic ranges (SFDRs)] in wide bandwidths (>100 MHz). However, at low frequencies ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\leq $ </tex-math></inline-formula> 10 MHz), their performance is limited by the 1/ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${f}$ </tex-math></inline-formula> noise generated by the near-minimum size devices used in their wide-bandwidth input stages. This, in turn, limits their use in radio receivers intended to cover both the AM and FM bands. In this work, a multi-path multi-frequency chopping scheme is proposed to suppress 1/ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${f}$ </tex-math></inline-formula> noise, while preserving interferer robustness, thermal noise levels, and linearity. Implemented in a CT <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Delta \Sigma $ </tex-math></inline-formula> analog-to-digital converter (ADC) sampling at 6 GHz, it achieves a 22 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> reduction in 1/ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${f}$ </tex-math></inline-formula> noise, as well as 122-dBFS SFDR and −98.3-dBc THD in a 120-MHz BW.

The full-wave rectifier is the most straightforward way of extracting energy from a piezoelectric source. Unfortunately, the inherent capacitance of the piezo source significantly limits the efficiency of extraction. The bias-flip rectifier, which aims to mitigate this problem, not only needs a large inductor for efficient operation, but also needs precise tuning. We present the multi-stage bias-flip rectifier, which is a technique that achieves a high voltage-flip efficiency using a smaller inductor and relaxes timing-accuracy requirements. The rectifier, implemented in a 130 nm CMOS process, dissipates about 2 μ W and achieves a voltage-flip efficiency of 90% while using an inductor of only 47 μH.